
Advanced packaging in semiconductor manufacturing is now growing faster than traditional front-end wafer fabrication. This indicates a significant shift in how chips are designed and produced, moving beyond just shrinking transistors. Concurrently, a new technology called NPO (likely a specific type of optical interconnect) has been developed to enable commercial CPO (Co-Packaged Optics).
This matters because advanced packaging is crucial for improving chip performance, power efficiency, and cost-effectiveness, especially as the limits of traditional scaling are approached. CPO, enabled by NPO, integrates optical communication directly with chips, drastically reducing latency and power consumption for data transfer. This is vital for handling the massive data flows in AI and high-performance computing.
The mechanism involves advanced packaging techniques like 3D stacking and chiplets, which allow different components to be integrated more densely and efficiently than traditional monolithic designs. CPO physically places optical transceivers much closer to the processing units, using NPO technology to facilitate this integration and enable reliable, high-speed optical data links within the same package.
This trend primarily moves semiconductor equipment manufacturers like ASML (ASML), KLA Corp (KLAC), and Lam Research (LRCX) as demand for advanced packaging tools rises. Chipmakers such as Nvidia (NVDA), AMD (AMD), Intel (INTC), and Broadcom (AVGO) are impacted as they adopt these technologies for AI chips and data center solutions, potentially lowering their power consumption and improving performance for their end customers.
An AI breakdown of exactly what changed and who it moves.